module generic_blk_mem #(
  parameter DEPTH=10
)(
  input clka,
  input [3:0] wea,
  input [DEPTH-1:0] addra,
  input [31:0] dina,
  output reg [31:0] douta,
  /* verilator lint_off UNUSED */
  input clkb, // ignored, treated as clka
  /* verilator lint_on UNUSED */
  input enb,
  /* verilator lint_off UNUSED */
  input [3:0] web, // ignored, treated as 4'b0
  /* verilator lint_on UNUSED */
  input [DEPTH-1:0] addrb,
  /* verilator lint_off UNUSED */
  input [31:0] dinb, // ignored
  /* verilator lint_on UNUSED */
  output reg [31:0] doutb
);

// Wrong endianness
//reg [31:0] m[0:2**DEPTH-1];
reg [31:0] m[0:2**DEPTH-1];

always @(posedge clka) begin
  // read port A
  douta <= m[addra];
  // write port A
  if (wea[0]) m[addra][ 7: 0/* 0: 7*/] <= dina[ 7: 0];
  if (wea[1]) m[addra][15: 8/* 8:15*/] <= dina[15: 8];
  if (wea[2]) m[addra][23:16/*16:23*/] <= dina[23:16];
  if (wea[3]) m[addra][31:24/*24:31*/] <= dina[31:24];
  // read port B
  if (enb) begin
    doutb <= m[addrb];
  end
end

endmodule
